This invention relates to wafer-level packaging techniques for semiconductor chips and in particular to packaging techniques for active or passive semiconductor chips that contain devices or components, such as vertical power MOSFETs or capacitors, that have terminals on both sides of the chip.
After the processing of a semiconductor wafer has been completed, the resulting semiconductor chips, which could be integrated circuit (IC) or MOSFET chips for example, must be separated and packaged in such a way that they can be connected to external circuitry. There are many known packaging techniques. Most involve mounting the chip on a leadframe, connecting the chip pads to the leadframe by wire-bonding or otherwise, and then encapsulating the chip and wire bonds in a plastic capsule, with the leadframe left protruding from the capsule. The encapsulation is often done by injection-molding. The leadframe is then trimmed to remove the tie bars that hold it together, and the leads are bent in such a way that the package can be mounted on a flat surface, typically a printed circuit board (PCB).
This is generally an expensive, time-consuming process, since the individual chips are typically handled separately. Moreover, the resulting semiconductor package is considerably larger than the chip itself, using up an undue amount of scarce xe2x80x9creal estatexe2x80x9d on the PCB. In addition, wire bonds are fragile and introduce a considerable resistance between the chip pads and the leads of the package.
The problems are particularly difficult when the device to be packaged is a xe2x80x9cverticalxe2x80x9d device, having terminals on opposite faces of the chip. For example, a power MOSFET typically has its source and gate terminals on the front side of the chip and its drain terminal on the back side of the chip. Similarly, a vertical diode has its anode terminal on one face of the chip and its cathode terminal on the opposite face of the chip. Bipolar transistors, junction field effect transistors (JFETs), and various types of integrated circuits (ICs) can also be fabricated in a xe2x80x9cverticalxe2x80x9d configuration, as can passive components such as semiconductor capacitors or resistors.
Accordingly, there is a need for a process which is simpler and less expensive than existing processes and which produces a package that is essentially the same size as the chip. There is a particular need for such a process and package that can be used with semiconductor dice having terminals on both their front and back sides. For reasons of economy and enhanced performance, it is desirable that the process be performed on all of the chips in the wafer form before they are separated from each other, i.e., that the process be vertical wafer-level chip-scale packaging.
All of these objectives are satisfied in a semiconductor chip package and method of fabricating the same in accordance with this invention.
A power MOSFET package in accordance with this invention comprises a semiconductor chip comprising a vertical power MOSFET. The power MOSFET comprises a source region and a gate electrode generally on a front side of the chip. A source contact, a gate contact and a drain contact are located adjacent the front side of the chip, the source contact being electrically connected to the source region, the gate contact being electrically connected to the gate, and the source, gate and drain contacts being electrically insulated from each other. One or more vias extend through the semiconductor chip from the front side to the back side, the vias being filled with a conductive material such as metal, the conductive material being electrically connected with the drain contact and a drain region of the MOSFET. The drain region may be located adjacent the back side of the MOSFET.
The source contact and the drain contact can each comprise pads, layers, bumps and other conductive elements.
In some embodiments, the vias are in the form of holes through the chip of a circular or other shape; in other embodiments, the vias are in the form of longitudinal trenches.
In some embodiments, a backside support substrate is attached to a back side of the semiconductor chip, the backside support substrate being electrically conductive, the conductive material being electrically connected with the backside support substrate
In some embodiments according to the invention, the vias extend partially into the semiconductor chip from the front side and terminate in the drain region. The vias do not extend all the way through the semiconductor chip. The vias are filled with metal or another conductive material, the conductive material being electrically connected with the drain contact.
The principles of this invention are not limited to semiconductor chips that contain power MOSFETs. Rather, the principles of this invention can be used with virtually any semiconductor IC device that has terminals on both sides of the chipxe2x80x94for example, vertical diodes, vertical bipolar transistors, and junction field effect transistors (JFETs). Thus, in another aspect of this invention, a semiconductor package comprises a semiconductor chip having first and second principal surfaces and comprising a vertical semiconductor device of any kind. The device has a first terminal located adjacent the first principal surface and a second terminal located adjacent the second principal surface. A first contact is located at the first principal surface of the semiconductor chip and is electrically connected to the first terminal of the device. A second contact is also located at the first principal surface. One or more vias extend at least part of the way through the semiconductor chip, the vias being filled with a conductive material and the conductive material being electrically connected to the second contact and the second terminal of the device. The vias may extend part of the way through the semiconductor chip or entirely through the semiconductor chip. The semiconductor package can comprise a support substrate attached to the second principal surface of the semiconductor chip. The support substrate may be electrically conductive and/or may be attached to the second principal surface of the semiconductor chip with an electrically conductive adhesive.
The invention also includes a process of fabricating a power MOSFET package in wafer form, the process comprising the steps of: providing a semiconductor wafer comprising a plurality of chips, each of the chips comprising a power MOSFET, each of the chips having a front side adjacent to which a source region and a gate electrode are located; forming a mask over a front side of the wafer, the mask having a plurality of openings; etching the wafer through the openings in the mask to form a plurality of vias extending through the wafer; depositing metal in the vias; and separating the chips from each other. The process may also include the steps of thinning the wafer, for example by grinding or lapping the back side of the wafer, and/or attaching a support substrate to a back side of the wafer. The support substrate can be electrically conductive.
The process may also include forming solder bumps in the openings for the source, gate and drain pads and insulating the solder bumps by forming, a passivation layer.
Alternatively, the wafer can be etched such that the vias extend only partially through the wafer, thereby making electrical contact between the metal in the vias and the drain of the power MOSFET.
According to yet another embodiment, the mask can be formed over the back side of the wafer, and the wafer can be etched through the openings in the mask from the back side to the front side of the wafer.
The process of this invention can be used to fabricate a package for any semiconductor device that has terminals on both sides of the chipxe2x80x94for example, vertical diodes, vertical bipolar transistors, and junction field effect transistors (JFETs). Thus the invention also includes a process of fabricating a package for any type of semiconductor device comprising: providing a semiconductor wafer comprising a plurality of chips, each of the chips comprising the semiconductor device, the wafer having first and second principal surfaces; the semiconductor device having a first terminal located adjacent the first principal surface and a second terminal located adjacent the second principal surface; forming a mask over the first principal surface of the wafer, the mask having a plurality of openings, there being at least one of the openings adjacent each of the chips; etching the wafer through the openings in the mask from the first principal surface to the second principal surface to form a plurality of vias extending entirely through the wafer; removing the mask; depositing an electrically conductive material in the vias; and separating the chips from each other.